The present invention relates in general to a flash memory cell and its memory array and, more particularly, to a self-aligned multi-bit flash memory cell and its contactless flash memory array.
A flash memory cell structure can be basically divided into two categories: a stack-gate structure and a split-gate structure, in which the stage-gate structure having the gate length of a cell defined by a minimum-feature size (F) of technology used is often used in existing high-density flash memory system. The stack-gate flash memory cells can be interconnected to form different circuit configurations based on the basic logic function, such as NOR, NAND and AND. A stack-gate flash memory cell can be programmed by channel hot-electron injection to have different threshold-voltage levels for a multi-bit storage. However, the endurance of the cell and the sensing of the threshold-voltage levels become a difficult task, especially the gate length of a stack-gate flash memory cell is scaled. Therefore, a dual-bit flash memory cell with two floating-gate structures becomes a major trend of developments.
FIG. 1A shows a cross-sectional view of a dual-bit flash memory cell, in which two stackgate transistors 22G, 20G spaced by a select-gate transistor 24G are formed on a semiconductor substrate 26; two common N+/Nxe2x88x92 diffusion regions 22A, 20A are separately formed in each side of the gate region; a select-gate line (SG) is formed above two common N+/Nxe2x88x92 diffusion regions and two stack-gate transistors and on a gate dielectric layer 24A being formed on a semiconductor substrate 26. Since the stackgate transistor, the select-gate transistor and the common N+/Nxe2x88x92 diffusion region can be defined by a masking photoresist step with a minimum-feature F, the cell size of each bit in a dual-bit flash memory cell can be designed to be equal to 4F2 if the select-gate line and its space can be defined to be a minimum-feature-size F. FIG. 1B shows a top plan view of a dual-bit flash memory cell shown in FIG. 1A. Apparently, the cell size of each bit shown in FIG. 1A and FIG. 1B can be made to be comparable to that of a NAND-type flash memory array due to the contactless structure. However, there are several drawbacks that can be easily observed from FIG. 1A and FIG. 1B: very high parasitic capacitance between the select-gate line (SG) and the common N+/Nxe2x88x92 diffusion regions 22A, 20A; very high parasitic capacitance between the select-gate line (SG) and the control-gate lines 22C, 20C; isolation between the common N+/Nxe2x88x92 diffusion regions is poor for the regions outside of the select-gate region 24A; and isolation between nearby select-gate lines is very poor for the regions under the control-gate lines 22C, 20C. It should be emphasized that poor isolation between nearby select-gate lines may result in an erroneous data reading from nearby cells under the same control-gate line.
It is therefore an objective of the present invention to provide a self-aligned multi-bit flash memory cell having a cell size of each bit being smaller than 2F2.
It is another objective of the present invention to provide a self-aligned multi-bit flash memory cell being programmed by a mid-channel hot-electron injection with much better programming efficiency and much smaller programming power.
It is a further objective of the present invention to provide a highly conductive common-source/drain bus line for each of bit-lines in a contactless multi-bit flash memory array with much smaller bit-line resistance and much smaller bit-line parasitic capacitance with respect to the semiconductor substrate and the word lines.
It is yet another objective of the present invention to provide a highly conductive metal line for each of word lines in a contactless multi-bit flash memory array with much smaller word-line resistance and much smaller word-line parasitic capacitance with respect to the bit-lines.
Other objectives and advantages of the present invention will be more apparent from the following description.
A self-aligned multi-bit flash memory cell and its contactless multi-bit flash memory array are disclosed by the present invention. The self-aligned multi-bit flash memory cell is formed on a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow-trench-isolation (STI) regions and can be divided into three regions: a common-source region, a gate region, and a common-drain region, in which the gate region is located between the common-source region and the common-drain region. The common-source/drain region comprises a first/second sidewall dielectric spacer being formed over each sidewall of the gate region and on a portion of a first/second flat bed being formed by a common-source/drain diffusion region and the etched first/second raised field-oxide layers, a common-source/drain conductive bus line being formed over the first/second flat bed outside of the first/second sidewall dielectric spacer, and a first/second planarized thick-oxide layer being formed over the common-source/drain conductive bus line and the first/second sidewall dielectric spacer. The gate region comprises a first floating-gate structure having a first floating-gate layer (FG1) formed on a first gate-dielectric layer and a second floating-gate structure having a second floating-gate layer (FG2) formed on a second gate-dielectric layer, wherein the first floating-gate structure and the second floating-gate structure being spaced with a spacing dielectric layer are formed in the active region; and a planarized control-gate layer (CG) over an intergate dielectric layer is at least formed over the first/second floating-gate structure, the spacing dielectric layer, the sidewalls of the first/second sidewall dielectric spacers, and the raised field-oxide layers for the first embodiment of the present invention. A first interconnect-metal layer is formed over the intergate-dielectric layers on the common-source/drain regions and the planarized control-gate layer (CG) to act as a word line, wherein the first interconnect-metal layer together with the planarized control-gate layer are simultaneously patterned by a masking dielectric layer and its two sidewall dielectric spacers. An implanted region of a first conductivity type is formed in a semiconductor substrate under the second floating-gate structure, wherein the implanted region comprises a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop. Similarly, if the intergate dielectric layer for the first embodiment of the present invention is replaced by an intergate-dielectric layer being only formed over the first/second floating-gate layers and the spacing dielectric layer in the active region, the self-aligned multi-bit flash memory cell becomes the second embodiment of the present invention.
A contactless multi-bit flash memory array of the present invention is formed on a semiconductor substrate of a first conductivity type having a plurality of parallel STI regions and a plurality of active regions formed alternately. A plurality of common-source bus-line regions and a plurality of virtual-gate regions are formed alternately and transversely to the plurality of parallel STI regions, wherein each of the plurality of virtual-gate regions comprises a pair of gate regions being located in each side portion and a common-drain bus-line region being located between the pair of gate regions. Each of the plurality of common-source bus-line regions comprises a pair of first sidewall dielectric spacers being formed over each sidewall of nearby virtual-gate regions and on a portion of a first flat bed being alternately formed by a common-source diffusion region of a second conductivity type and an etched first raised field-oxide layer; a common-source conductive bus line being formed over the first flat bed between the pair of first sidewall dielectric spacers; and a first planarized thick-oxide layer being formed over the common-source conductive bus line and the pair of first sidewall dielectric spacers. Each of the common-drain bus-line regions comprises a pair of second sidewall dielectric spacers being formed over each sidewall of nearby gate regions and on a portion of a second flat bed being alternately formed by a common-drain diffusion region and an etched second raised field-oxide layer; a common-drain conductive bus line being formed over the second flat bed between the pair of second sidewall dielectric spacers; and a second planarized thick-oxide layer being formed over the common-drain conductive bus line and the pair of second sidewall dielectric spacers. Each of the pair of gate regions comprises a plurality of first floating-gate layers being formed over a plurality of first gate-dielectric layers in a side portion of the plurality of active regions and a plurality of second floating-gate layers being formed over a plurality of second gate-dielectric layers in another side portion of the plurality of active regions with a spacing dielectric layer being formed between each of the first floating-gate layer over the first gate-dielectric layer and each of the second floating-gate layer over the second gate-dielectric layer; a plurality of planarized control-gate layers together with a plurality of first interconnect-metal layers being simultaneously patterned and etched to form a plurality of word lines transversely to the plurality of common-source/drain conductive bus lines. An intergate dielectric layer is at least formed over the first/second floating-gate layers, the spacing dielectric layers, the first/second planarized thick-oxide layers, the first/second sidewall dielectric spacers, and the raised field-oxide layers in each of the gate regions for the first embodiment of the present invention, wherein each of the plurality of word lines is formed over the intergate dielectric layer on the plurality of common-source/drain bus-line regions. However, the intergate-dielectric layer is only formed over the first/second floating-gate layers and the spacing dielectric layer in each of the active regions for the second embodiment of the present invention.